GC5330多天线宽带数字发送和接收 解决方案

The GC533x is a wideband transmit and receive signal processor that includes digital downconverter / upconverter (DDUC), transmit, receive, and capture buffer blocks. The transmit path includes crest factor reduction (CFR), digital predistortion (DPD) and associated feedback path, complex equalization, and bulk upconversion.

The receive path includes wideband and narrowband automatic gain control (AGC), bulk downconversion, complex equalization, and I/Q imbalance correction.

The DDUC section consists of four identical DDUC blocks, each supporting up to 12 channels. Each channel has independent fractional resamplers and NCOs to enable flexible carrier configurations. Multi-mode/multi-standard operation can be supported by configuring the inpidual DDUC blocks to different filtering and oversampling scenarios.

The CFR block reduces the peak-to-average ratio (PAR) of the digital transmit signals, such as those used in third-generation (3G) code pision multiple access (CDMA) and orthogonal frequency-pision multiple-access (OFDMA) applications.

The DPD path with a 310-MHz DPD clock can be configured to support one antenna at 62 MHz, two antennas at 62 MHz each, or four antennas at 31 MHz each, all with an associated 5× DPD expansion bandwidth. The GC533x DPD processor reduces power amplifier (PA) nonlinearity, e.g., as measured by adjacent-channel leakage ratio (ACLR), by over 20 dB. By reducing the PAR of the digital signal and the PA nonlinearity, the operational efficiency of follow-on power amplifiers can be substantially improved.

A higher DPD bandwidth is possible with reduced DPD performance.