RF 模组 SGN6210DDA DICE

RF 模组 SGN6210DDA DICE

Product Description:

The Signia SGN6210 IC is a low-cost, fully integrated CMOS radio frequency (RF) transceiver block, combined with a 64-byte buffered framer block. In normal applications, the SGN6210 is connected to a low-cost microcomputer (MCU).

The on-chip framer processes and stores the RF data in the background, unloading this critical timing function from the MCU. This lowers MCU speed requirements, expedites product development time, and frees the MCU for

implementing additional product features. The RF transceiver block is a self-contained, fast-hopping GFSK data modem, optimized for use in the widely available 2.4 GHz ISM band. It contains transmit, receive, VCO and PLL

functions, including an on-chip channel filter and resonator, thus minimizing the need for external components. The

receiver utilizes extensive digital processing for excellent overall performance, even in the presence of interference and transmitter impairments. Transmit power is digitally controlled The low-IF receiver architecture results in sensitivity to -80 dBm or better, with impressive selectivity.

The framer register settings determine the over-the-ai formatting characteristics. Transmit data is easily sent overthe- air as a complete frame of data, with preamble, address, payload, and CRC. Receiving data is just the opposite, using the preamble to train the receiver clock recovery, then the address is checked, then the data is reverse formatted for receive, followed by CRC. All of this is done in hardware to ease the programming and overhead requirements of the baseband MCU. For longer battery life, power consumption is minimized by automatic enabling of the various transmit, receive, PLL, and PA sections, depending on the instantaneous state of the chip.

A sleep mode is also provided for ultra low current consumption.

This product is supplied in lead-free, RoHS compliant, 32-lead 5x5 mm JEDEC standard QFN package, featuring an exposedpad on the bottom for best RF characteristics.

Key Features:

• Combines 2.4 GHz GFSK RF transceiver with

8-bit data framer function

• Eliminates need for external software or

hardware FIFO; offloads MCU for other tasks

• Simple microprocessor interface – 4 wires for

SPI, plus 3 wires for RST/buffer control

• Each transmit, receive buffer is 64 bytes deep

• Long packets are possible if buffers are

read/written before overflow/underflow occurs

• Always 1 Mbps over-the-air symbol rate,

regardless of MCU speed or architecture

• Preamble can be 1 to 8 bytes

• Supports 1, 2, 3, or 4 word address (up to 64

bits)

• Various Payload data formats to eliminate DC

offset, enhance receive clock recovery and BER

• Programmable data whitening

• Supports Forward Error Correction (FEC):

none, 1/3, or 2/3

• Supports 16-bit CRC

• Power management for minimizing current

consumption

• Lead-free 5x5mm QFN package

with minimum RF parasitics

Applications:

• Wireless devices that need quick time-to-market

• Battery Powered wireless devices

• Wireless streaming audio

• Home and factory automation

• Simple and fast wireless data networks

• Cordless headsets and Cellular Phones

• Wireless voice and VOIP

• Wireless security and access control

IR Reflow Standard

Follow : IPC/JEDEC J-STD-020 B

Condition : Average ramp-up rate (183ºC to peak): 3 ºC/sec. max.

Preheat: 100~150ºC 60~120sec

Temperature maintained above 183ºC: 60~150 seconds

Time within 5ºC of actual peak temperature: 10 ~ 30 sec.

Peak temperature: 240+0/-5 ºC

Ramp-down rate: 6 ºC/sec. max.

Time 25ºC to peak temperature: 6 minutes max.

Cycle interval: 5 minutes

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