-N沟道场效应管 SI2302

VDS= 20V

RDS(ON), Vgs@-2.5V, Ids@2.0A = 90m?@TYP

RDS(ON), Vgs@4.5V, Ids@3.2A = 65m?@TYP

Features

Advanced trench process technology

High Density Cell Design For Ultra Low On-Resistance

SOT-23 Internal Schematic Diagram

Top View N-Channel MOSFET

Maximum Ratings and Thermal Characteristics(TA=25℃unless otherwise noted)ParameterSymbolLimitUnitDrain-Source VoltageVDS20VGate-Source VoltageVGS±8Continuous Drain CurrentID2.3APulsed Drain Current1)IDM8Maximum Power DissipationTA=25℃PD1.25WTA=75℃0.8Operating Junction and Storage Temperature RangeTJ, Tstg-55 to 150℃Junction-to-Ambient Thermal Resistance (PCB mounted)2)RθJA140℃/WNote: 1. Repetitive Rating: Pulse width limited by the maximum junction temperature

2. 1-in22oz Cu PCB board

Electrical CharacteristicsParameterSymbolTest ConditionMinTypMaxUnitStaticDrain-Source Breakdown VoltageBVDSSVGS= 0V, ID= 250uA20----VDrain-Source On-Stage ResistanceRDS(on)VGS= 4.5V, ID= 2.8A--40.060.0mΩDrain-Source On-Stage ResistanceRDS(on)VGS= 2.5V, ID= 2.0A--50.0115.0Drain-Source On-Stage ResistanceRDS(on)VGS= 1.8V, ID= 2.0A--80.0130.0Gate Threshold VoltageVGS(th)VDS= VGS, ID= 250uA0.6--1.2VZero Gate Voltage Drain CurrentIDSSVDS= 20V, VGS= 0V----1uAGate Body LeakageIGSSVGS=±8V, IDS=0uA----±100nADynamic3)Total Gate ChargeQgVDS= 10V, ID= 3.6A

VGS= 4.5V--4.55.85nCGate-Source ChargeQgs--0.831.08Gate-Drain ChargeQgd--1.181.53Turn-On Delay Timetd(on)VDD= 15V, RL= 5.5Ω

ID= 1A, VGEN= 4.5V

RG= 6Ω--11.2422.48nsTurn-On Rise Timetr--3.486.96Turn-Off Delay Timetd(off)--19.6439.28Turn-Off Fall Timetf--4.48.8Input CapacitanceCissVDS= 10V, VGS= 0V

f=1.0MHz--456.41--pFOutput CapacitanceCoss--86.81--Reverse Transfer CapacitanceCrss--58.89--Source-Drain DiodeMax. Diode Forward CurrentIS------1.6ADiode Forward VoltageVSDIS= 1.6A, VGS= 0V----1.2VNote: Pulse test: pulse width <= 300us, duty cycle<= 2%

3. Guaranteed by design; not subject to production testing